MC9S12UF32 Datasheet, PDF (56/128 Pages) Freescale Semiconductor, Inc – System on a Chip Guide V01.05

System on a Chip Guide — 9S12UF32DGV1/D V01.05
Internal Pull
Pin Name
Function
1
Pin Name
Function
2
Pin Name
Function
3
Pin Name
Function
4
Pin Name
Function
5
Supply
Rail
Resistor
CTRL
Reset
State
Description
PQ4
PQ3
PQ2
SDAT4
SDAT3
SDAT2
CFA4 ATADMACK IOC4
CFIORD ATAIORD
—
CFA2
ATADA2
—
VDD3X
VDD3X
VDD3X
Port Q I/O Pins; SMHC Data
PERQ/
PPSQ
Disabled
line; CFHC address line;
ATA5HC DMACK signal; Timer
Channel
PERQ/
PPSQ
Disabled
Port Q I/O Pins; SMHC Data line,
CFHC CFIORD signal; ATA5HC
ATAIORD signal
PERQ/
PPSQ
Disabled
Port Q I/O Pins; SMHC Data
line; CFHC Address signal; ATA
Address signal
PQ1
SDAT1
CFA1
ATADA1
PQ0
PS7
SDAT0
CFA0
ATADA0
MSSDIO
CFRDY/
IREQ
ATAINTQ
—
VDD3X
PERQ/
PPSQ
Disabled
Port Q I/O Pins; SMHC Data
line; CFHC Address signal; ATA
Address signal
—
VDD3X
PERQ/
PPSQ
Disabled
Port Q I/O Pins; SMHC Data
line; CFHC Address signal; ATA
Address signal
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC RDYIREQ
signal; ATA INTQ signal; MSHC
serial data I/O.
PS6
MSSCLK CFWE ATADMARQ
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; CFHC WE signal;
ATA DMARQ signal; MSHC
serial clock.
PS5
TXD
—
—
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; SCI TXD.
PS4
RXD
—
—
—
VDDX
PERS/
PPSS
Disabled
Port S I/O Pin; SCI RXD.
PT1
SWE
CFOE SDDATA3
IOC1
VDD3X
PERT/
PPST
Port T I/O Pins; SMHC SWE
Disabled signal; CFHC CFOE signal;
SDHC data; Timer channel;
PT0
SRE
CFREG SDDATA0
IOC0
VDD3X
PERT/
PPST
Port T I/O Pins; SMHC SRE
Disabled signal; CFHC CFREG signal;
SDHC data; Timer channel;
PU0
SCD
CFWAIT ATAIORDY
—
VDDX
PERU/
PPSU
Disabled
Port U I/O Pins; CFHC WAIT
signal; ATA IORDY signal; SMHC
SCD signal.
NOTES:
1. This pin must be tied to VSS in Application
2. PJ2 is used as the ROMCTL signal during reset.
56
Freescale Semiconductor