MC908AZ32ACFUE Datasheet, PDF (93/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
Register Name
Read:
PLL Control Register
(PCTL)
Write:
Reset:
Read:
PLL Bandwidth Control Register
(PBWC)
Write:
Reset:
Read:
PLL Programming Register
(PPG)
Write:
Reset:
Bit 7
6
5
4
3
PLLF
1
PLLIE
PLLON
BCS
0
0
1
0
1
LOCK
0
AUTO
ACQ
XLD
0
0
0
0
0
MUL7
MUL6
MUL5
MUL4
VRS7
0
1
1
0
0
= Unimplemented
Figure 8-2. I/O Register Summary
Table 8-1. I/O Register Address Summary
Register
Address
PCTL
$001C
PBWC
$001D
PPG
$001E
2
1
1
0
0
VRS6
1
1
1
1
0
0
VRS5
1
Bit 0
1
1
0
0
VRS4
0
8.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
8.3.2.1 Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f_CGMVRS. Modulating the voltage on the
CGMXFC pin changes the frequency within this range. By design, f_CGMVRS is equal to the nominal
center-of-range frequency, f_NOM, (4.9152 MHz) times a linear factor L or (L)f_NOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f_CGMRCLK, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV,
running at a frequency f_CGMRDV = f_CGMRCLK.
The VCO’s output clock, CGMVCLK, running at a frequency f_CGMVCLK, is fed back through a
programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider’s
output is the VCO feedback clock, CGMVDV, running at a frequency f_CGMVDV = f_CGMVCLK/N. See 8.3.2.4
Programming the PLL for more information.
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock,
CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
93