MC908AZ32ACFUE Datasheet, PDF (285/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

24.13.3 MSCAN08 Bus Timing Register 0
Programmer’s Model of Control Registers
Address:
Read:
Write:
Reset:
$0502
Bit 7
6
5
4
3
2
1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
0
0
0
0
0
0
0
Figure 24-17. Bus Timing Register 0 (CBTR0)
Bit 0
BRP0
0
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time quanta (T_q) clock cycles
by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 24-6).
Table 24-6. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization
Jump Width
1 T_q cycle
2 T_q cycle
3 T_q cycle
4 T_q cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T_q) clock, which is used to build up the individual bit timing,
according to Table 24-7.
BRP5
0
0
0
0
:
:
1
Table 24-7. Baud Rate Prescaler
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler
Value (P)
1
2
3
4
:
:
64
NOTE
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08
module control register is set.
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
285