MC908AZ32ACFUE Datasheet, PDF (134/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

External Interrupt Module (IRQ1)
ACK
VECTOR
FETCH
DECODER
V_DD
CLR
D
Q
IRQ1
CK
IRQ
LATCH
SYNCHRO-
NIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
Figure 15-1. IRQ Block Diagram
TO MODE
SELECT
LOGIC
Addr.
$001A
Register Name
Bit 7
6
5
4
3
IRQ Status/Control Register ^{Read: 0}
0
0
0
IRQF
(ISCR) _{Write: R}
R
R
R
R
R = Reserved
Figure 15-2. IRQ I/O Register Summary
2
1
Bit 0
0
IMASK MODE
ACK
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the ISCR masks all external interrupt requests. A latched interrupt request is
not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See Figure 15-3).
MC68HC908AZ32A Data Sheet, Rev. 2
134
Freescale Semiconductor