MC908AZ32ACFUE Datasheet, PDF (196/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module A (TIMA)
18.6 TIMA During Break Interrupts
A break interrupt stops the TIMA counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state (see 7.7.3 SIM Break Flag Control Register).
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
18.7 I/O Signals
Port D shares one of its pins with the TIMA. Port E shares two of its pins with the TIMA and port F shares
four of its pins with the TIMA. PTD6/ATD14/TCLK is an external clock input to the TIMA prescaler. The
six TIMA channel I/O pins are PTE2/TCH0, PTE3/TCH1, PTF0/TCH2, PTF1/TCH3, PTF2/TCH4, and
PTF3/TCH5.
18.7.1 TIMA Clock Pin (PTD6/ATD14/TACLK)
PTD6/ATD14/TCLK is an external clock input that can be the clock source for the TIMA counter instead
of the prescaled internal bus clock. Select the PTD6/ATD14/TCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0] (see 18.8.1 TIMA Status and Control Register). The minimum TCLK pulse
width, TCLK_LMIN or TCLK_HMIN, is:
------------------1-------------------
bus frequency
+
tSU
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC channel when not used as the TIMA
clock input. When the PTD6/ATD14/TCLK pin is the TIMA clock input, it is an input regardless of the state
of the DDRD6 bit in data direction register D.
18.7.2 TIMA Channel I/O Pins (PTF3/TCH5–PTF0/TCH2 and PTE3/TCH1–PTE2/TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
PTE2/TCH0, PTF0/TACH2 and PTF2/TCH4 can be configured as buffered output compare or buffered
PWM pins.
MC68HC908AZ32A Data Sheet, Rev. 2
196
Freescale Semiconductor