MC908AZ32ACFUE Datasheet, PDF (201/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
Register Name and Address
Bit 7
6
Read: CH4F
Write: 0
CH4IE
Reset: 0
0
TASC4 — $0032
5
4
MS4B MS4A
0
0
3
ELS4B
0
2
ELS4A
0
1
Bit 0
TOV4 CH4MAX
0
0
Register Name and Address
TASC5 — $0035
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH5F
0
CH5IE
MS5A ELS5B ELS5A TOV5 CH5MAX
Write: 0
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 18-7. TIMA Channel Status
and Control Registers (TASC0–TASC5) (Continued)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
When CHxIE = 1, clear CHxF by reading TIMA channel x status and control register with CHxF set and
then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMA
channel 0, TIMA channel 2 and TIMA channel 4 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TACH1 pin to
general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and reverts TACH3 pin to
general-purpose I/O.
Setting MS4B disables the channel 5 status and control register and reverts TACH5 pin to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
201