MC908AZ32ACFUE Datasheet, PDF (110/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG-1)
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. (See Chapter 14 Low Voltage Inhibit (LVI)).
1 = LVI module resets enabled
0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. (See Chapter 14 Low Voltage Inhibit (LVI)).
1 = LVI module power enabled
0 = LVI module power disabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay. (See 7.6.2 Stop Mode).
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE
If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS enables the shorter COP timeout period. (See Chapter 13 Computer Operating Properly
(COP).
1 = COP timeout period is 8176 CGMXCLK cycles
0 = COP timeout period is 262,128 CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).
1 = COP module disabled
0 = COP module enabled
CAUTION
Extra care should be exercised when using this emulation part for
development of code to be run in ROM AZ or AB parts that the options
selected by setting the CONFIG-1 register match exactly the options
selected on any ROM code request submitted. The enable/disable logic is
not necessarily identical in all parts of the AZ and AB families. If in doubt,
check with your local field applications representative.
MC68HC908AZ32A Data Sheet, Rev. 2
110
Freescale Semiconductor