MC908AZ32ACFUE Datasheet, PDF (281/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

DLC3
0
0
0
0
0
0
0
0
1
Programmer’s Model of Control Registers
Table 24-5. Data Length Codes
Data Length Code
DLC2
DLC1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
DLC0
0
1
0
1
0
1
0
1
0
Data Byte
Count
0
1
2
3
4
5
6
7
8
24.12.4 Data Segment Registers (DSRn)
The eight data segment registers contain the data to be transmitted or received. The number of bytes to
be transmitted or being received is determined by the data length code in the corresponding DLR.
24.12.5 Transmit Buffer Priority Registers
Address:
Read:
Write:
Reset:
$05bD
Bit 7
6
5
4
3
2
1
PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1
u
u
u
u
u
u
u
Figure 24-13. Transmit Buffer Priority Register (TBPR)
Bit 0
PRIO0
u
PRIO7–PRIO0 — Local Priority
This field defines the local priority of the associated message buffer. The local priority is used for the
internal prioritisation process of the MSCAN08 and is defined to be highest for the smallest binary
number. The MSCAN08 implements the following internal prioritisation mechanism:
• All transmission buffers with a cleared TXE flag participate in the prioritisation right before the SOF
is sent.
• The transmission buffer with the lowest local priority field wins the prioritisation.
• In case more than one buffer has the same lowest priority, the message buffer with the lower index
number wins.
24.13 Programmer’s Model of Control Registers
The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 24-14 gives an
overview on the control register block of the MSCAN08.
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
281