MC908AZ32ACFUE Datasheet, PDF (231/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
one conversion will take between 16 and 17 μs and there will be between 128 bus cycles between each
conversion. Sample rate is approximately 60 kHz.
Refer to 25.1.6 ADC Characteristics.
16 to 17 ADC Clock Cycles
Conversion Time = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ADC Clock Frequency
Number of Bus Cycles = Conversion Time x Bus Frequency
21.3.4 Continuous Conversion
In the continuous conversion mode, the ADC data register will be filled with new data after each
conversion. Data from the previous conversion will be overwritten whether that data has been read or not.
Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO
bit is set after the first conversion and will stay set for the next several conversions until the next write of
the ADC status and control register or the next read of the ADC data register.
21.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes. See 25.1.6 ADC Characteristics for
accuracy information.
21.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic
0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete
flag when interrupts are enabled.
21.5 Low-Power Modes
The following subsections describe the low-power modes.
21.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the
WAIT instruction.
21.5.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
231