MC908AZ32ACFUE Datasheet, PDF (137/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

IRQ Status and Control Register
15.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has these functions:
• Shows the state of the IRQ interrupt flag
• Clears the IRQ interrupt latch
• Masks IRQ interrupt request
• Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
Read:
Write:
Reset:
$001A
Bit 7
6
5
4
3
2
1
0
0
0
0
IRQF
0
IMASK
R
R
R
R
R
ACK
0
0
0
0
0
0
0
R
= Reserved
Figure 15-4. IRQ Status and Control Register (ISCR)
Bit 0
MODE
0
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears
ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE.
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
137