MC908AZ32ACFUE Datasheet, PDF (75/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7
System Integration Module (SIM)
7.1 Introduction
This section describes the system integration module (SIM), which supports up to 32 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all MCU activities. A
block diagram of the SIM is shown in Figure 7-2. Figure 7-1 is a summary of the SIM input/output (I/O)
registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is
responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Register Name
Bit 7
6
5
4
3
2
SIM Break Status Register (SBSR)
R
R
R
R
R
R
SIM Reset Status Register (SRSR) POR
PIN
COP
ILOP
ILAD
0
SIM Break Flag Control Register (SBFCR) BCFE
R
R
R
R
R
R
= Reserved
Figure 7-1. SIM I/O Register Summary
Table 7-1. I/O Register Address Summary
Register
Address
SBSR
$FE00
SRSR
$FE01
SBFCR
$FE03
1
Bit 0
BW
R
LVI
0
R
R
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
75