MC908AZ32ACFUE Datasheet, PDF (218/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module B (TIMB)
Register Name and Address
Bit 7
6
Read: CH0F
Write: 0
CH0IE
Reset: 0
0
TBSC0 — $0045
5
4
MS0B MS0A
0
0
3
ELS0B
0
2
ELS0A
0
1
Bit 0
TOV0 CH0MAX
0
0
Register Name and Address
TBSC1 — $0048
Bit 7
6
5
4
3
2
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A
Write: 0
R
Reset: 0
0
0
0
0
0
R
Reserved
Figure 19-7. TIMB Channel Status
and Control Registers (TBSC0–TBSC1)
1
TOV1
0
Bit 0
CH1MAX
0
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMB counter registers matches the value in the TIMB channel x registers.
When CHxIE = 1, clear CHxF by reading TIMB channel x status and control register with CHxF set,
and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due
to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIMB
channel 0.
Setting MS0B disables the channel 1 status and control register and reverts TBCH1 to
general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MC68HC908AZ32A Data Sheet, Rev. 2
218
Freescale Semiconductor