MC908AZ32ACFUE Datasheet, PDF (106/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield
nominal values under the following conditions:
• Correct selection of filter capacitor, C_F (see 8.9.3 Choosing a Filter Capacitor).
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters. K_acq is the K factor when the PLL
is configured in acquisition mode, and K_trk is the K factor when the PLL is configured in tracking mode.
(See 8.3.2.2 Acquisition and Tracking Modes).
t_acq
=
⎛
⎝
f--_C^---V_G^----_M^D---D_R^--A-_D^---_V^{-⎠⎞}
⎛
⎝
-K----_A^8---_C---_Q-_⎠⎞
t_al
=
⎛
⎝
f--_C^---V_G^----_M^D---D_R^--A-_D^---_V^{-⎠⎞}
⎛
⎝
-K----_T^4--_R---_K-_⎠⎞
t_Lock = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See 8.3.2.3 Manual and Automatic PLL Bandwidth Modes). A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, Δ_TRK,
before exiting acquisition mode. A certain number of clock cycles, n_TRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, Δ_Lock. Therefore, the acquisition time, t_ACQ, is an integer
multiple of n_ACQ/f_CGMRDV, and the acquisition to lock time, t_AL, is an integer multiple of n_TRK/f_CGMRDV.
Also, since the average frequency over the entire measurement period must be within the specified
tolerance, the total time usually is longer than t_Lock as calculated above.
In manual mode, it is usually necessary to wait considerably longer than t_Lock before selecting the PLL
clock (see 8.3.3 Base Clock Selector Circuit), because the factors described in 8.9.2 Parametric
Influences on Reaction Time, may slow the lock time considerably.
When defining a limit in software for the maximum lock time, the value must allow for variation due to all
of the factors mentioned in this section, especially due to the C_F capacitor and application specific
influences.
The calculated lock time is only an indication and it is the customer’s responsibility to allow enough of a
guard band for their application. Prior to finalizing any software and while determining the maximum lock
time, take into account all device to device differences. Typically, applications set the maximum lock time
as an order of magnitude higher than the measured value. This is considered sufficient for all such device
to device variation.
Freescale recommends measuring the lock time of the application system by utilizing dedicated software,
running in FLASH, EEPROM or RAM. This should toggle a port pin when the PLL is first configured and
switched on, then again when it goes from acquisition to lock mode and finally again when the PLL lock
MC68HC908AZ32A Data Sheet, Rev. 2
106
Freescale Semiconductor