MC908AZ32ACFUE Datasheet, PDF (109/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9
Configuration Register (CONFIG-1)
9.1 Introduction
This section describes the configuration register (CONFIG-1), which contains bits that configure these
options:
• Resets caused by the LVI module
• Power to the LVI module
• LVI enabled during stop mode
• Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
• Computer operating properly module (COP)
• STOP instruction enable/disable.
9.2 Functional Description
The configuration register is a write-once register. Out of reset, the configuration register will read the
default value. Once the register is written, further writes will have no effect until a reset occurs.
NOTE
If the LVI module and the LVI reset signal are enabled, a reset occurs when
V_DD falls to a voltage, LVI_TRIPF, and remains at or below that level for at
least nine consecutive CPU cycles. Once an LVI reset occurs, the MCU
remains in reset until V_DD rises to a voltage, LVI_TRIPR.
Address: $001F
Bit 7
6
Read:
LVISTOP
R
Write:
5
4
3
2
LVIRST LVIPWR SSREC COPRS
1
STOP
Bit 0
COPD
Reset: 0
1
1
1
0
0
0
0
R
= Reserved
Figure 9-1. Configuration Register (CONFIG-1)
LVISTOP — LVI Stop Mode Enable Bit
LVISTOP enables the LVI module in stop mode. (See Chapter 14 Low Voltage Inhibit (LVI)).
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
NOTE
To have the LVI enabled in stop mode, the LVIPWR must be at a logic 1
and the LVISTOP bit must be at a logic 1. Take note that by enabling the
LVI in stop mode, the stop I_DD current will be higher.
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
109