MC908AZ32ACFUE Datasheet, PDF (125/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 13
Computer Operating Properly (COP
13.1 Introduction
The COP module contains a free-running counter that generates a reset if allowed to overflow. The COP
module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP
counter.
13.2 Functional Description
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler. If not cleared by software,
the COP counter overflows and generates an asynchronous reset after 8176 or 262,128 CGMXCLK
cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG-1 register. When
COPRS = 0, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location
$FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 4–12 of
the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status
register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ pin is held at V_Hi. During the break
state, V_Hi on the RST pin disables the COP.
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
125