MC908AZ32ACFUE Datasheet, PDF (115/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Break Module Registers
11.4.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break wait bit (BW) in the SIM break status
register indicates whether wait was exited by a break interrupt. If so, the user can modify the return
address on the stack by subtracting one from it. See 7.7.1 SIM Break Status Register.
11.4.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
11.5 Break Module Registers
These registers control and monitor operation of the break module:
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status and control register (BSCR)
11.5.1 Break Status and Control Register
The break status and control register contains break module enable and status bits.
Address: $FE0B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. Break Status and Control Register (BSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to
BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
115