MC908AZ32ACFUE Datasheet, PDF (133/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15
External Interrupt Module (IRQ1)
15.1 Introduction
This section describes the nonmaskable external interrupt (IRQ) input.
15.2 Features
Features include:
• Dedicated External Interrupt Pin (IRQ1)
• Hysteresis Buffer
• Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity
• Automatic Interrupt Acknowledge
15.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 15-1 shows the
structure of the IRQ module.
Interrupt signals on the IRQ1 pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK bit clears the IRQ
latch.
• Reset — A reset automatically clears both interrupt latches.
The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge
and low-level triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ1 pin.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
133