MC908AZ32ACFUE Datasheet, PDF (87/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Registers
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 7-15 shows stop mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-15. Stop Mode Entry Timing
CGMXCLK
STOP RECOVERY PERIOD
INT/BREAK
IAB
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 7-16. Stop Mode Recovery from Interrupt or Break
7.7 SIM Registers
The SIM has three memory mapped registers.
7.7.1 SIM Break Status Register
The SIM break status register contains a flag to indicate that a break caused an exit from wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BW
R
R
R
R
R
R
R
Write:
See Note
Reset:
0
R
= Reserved
NOTE: Writing a 0 clears BW
Figure 7-17. SIM Break Status Register (SBSR)
BW — SIM Break Wait
This status bit is useful in applications requiring a return to wait mode after exiting from a break
interrupt. Clear BW by writing a 0 to it. Reset clears BW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
MC68HC908AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
87