MC908AZ32ACFUE Datasheet, PDF (102/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N.
(See 8.3.2.1 Circuits and 8.3.2.4 Programming the PLL). A value of $0 in the multiplier select bits
configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to
give a default multiply value of 6.
See Table 8-3.
NOTE
The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
Table 8-3. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L, which controls the
hardware center-of-range frequency, f_VRS. (See 8.3.2.1 Circuits, 8.3.2.4 Programming the PLL, and
8.5.1 PLL Control Register.) VRS7–VRS4 cannot be written when the PLLON bit in the PLL control
register (PCTL) is set. See 8.3.2.5 Special Programming Exceptions. A value of $0 in the VCO range
select bits disables the PLL and clears the BCS bit in the PCTL. (See 8.3.3 Base Clock Selector Circuit
and 8.3.2.5 Special Programming Exceptions for more information.) Reset initializes the bits to $6 to
give a default range multiply value of 6.
NOTE
The VCO range select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1) and prevents selection of the
VCO clock as the source of the base clock (BCS = 1) if the VCO range
select bits are all clear. The VCO range select bits must be programmed
correctly. Incorrect programming can result in failure of the PLL to achieve
lock.
MC68HC908AZ32A Data Sheet, Rev. 2
102
Freescale Semiconductor