MC908AZ32ACFUE Datasheet, PDF (78/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
7.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 7.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR) (see 7.7 SIM Registers).
7.3.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register
(SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither
the POR nor the LVI was the source of the reset. See Table 7-3 for details. Figure 7-4 shows the relative
timing.
Table 7-3. PIN Bit Set Timing
Reset Type
POR/LVI
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 7-4. External Reset Timing
MC68HC908AZ32A Data Sheet, Rev. 2
78
Freescale Semiconductor