MC908AZ32ACFUE Datasheet, PDF (114/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Brake Module
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Break Address Register High
(BRKH)
Write:
Bit 15
14
13
12
11
10
Reset: 0
0
0
0
0
0
9
Bit 8
0
0
Read:
Break Address Register Low
(BRKL)
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 0
0
0
0
0
0
0
0
Read:
0
0
0
0
0
0
Break Status and Control
Register (BSCR)
Write:
BRKE
BRKA
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. I/O Register Summary
Table 11-1. I/O Register Address Summary
Register
Address
BRKH
$FE0C
BRKL
$FE0D
BSCR
$FE0B
11.3.1 Flag Protection During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the
break state.
11.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
11.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
11.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_Hi is present on the RST pin.
11.4 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
MC68HC908AZ32A Data Sheet, Rev. 2
114
Freescale Semiconductor