MC908AZ32ACFUE Datasheet, PDF (80/324 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
OSC1
PORRST
CGMXCLK
4096
CYCLES
32
CYCLES
32
CYCLES
CGMOUT
RST
IAB
$FFFE
$FFFF
Figure 7-7. POR Recovery
7.3.2.2 Computer Operating Properly (COP) Reset
The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status
register (SRSR) if the COPD bit in the CONFIG-1 register is at logic zero. See Chapter 13 Computer
Operating Properly (COP.
7.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the CONFIG-1 register is logic zero, the SIM treats the STOP instruction
as an illegal opcode and causes an illegal opcode reset.
7.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
NOTE
Extra care should be exercised if code in this part has been migrated from
older HC08 devices since the illegal address reset specification may be
different. Also, extra care should be exercised when using this emulation
part for development of code to be run in ROM AZ, AB or AS family parts
with a smaller memory size since some legal addresses will become illegal
addresses on the smaller ROM memory map device and may as a result
generate unwanted resets.
MC68HC908AZ32A Data Sheet, Rev. 2
80
Freescale Semiconductor