MC68HC05X16 Datasheet, PDF (84/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
5.3.14 Remote transmission request and data length code
register (RRTDL)
The layout of this register is identical to the TRTDL register (see Section 5.3.11).
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
RTR and data length code (RRTDL) $0035 ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 Undefined
5.3.15 Receive data segment registers (RDS) 1 – 8
5
The layout of these registers is identical to the TDSx registers (see Section 5.3.12).
Receive data segment (RDS)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0036 –
$003D
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
(Note that there are actually two receive buffer register sets, but switching between them is
handled internally by the MCAN.)
5.4
Interface to the MCAN bus
Physically, the MCAN bus may be composed of two wires. The bus can take on one of two values:
dominant or recessive. During simultaneous transmission of dominant and recessive bits by two
or more CAN modules the resulting bus value will be dominant. (For example, with a wired-AND
implementation of the bus, the dominant level would correspond to a logic 0, and the recessive
level to a logic 1.)
The two wires of the MCAN bus are designated CANH and CANL. The voltage levels appearing
on these lines are designated V_CANH and V_CANL. A simple termination network is required for each
wire. Figure 5-6 shows the physical interface circuitry within the MCAN module, and its connection
to the MCAN bus with a typical low speed (<125 kbaud) hardware interface. (Note that the
suggested values shown in the diagram are subject to change in the future.)
For the voltage and resistor values shown in Figure 5-6 the voltages on the MCAN bus are:
– Recessive level:
– Dominant level:
V_CANH = 3.25 V
V_CANH = 1.00 V
V_CANL = 1.75 V
V_CANL = 4.00 V
MOTOROLA CAN MODULE (MCAN)
MC68HC05X16
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