MC68HC05X16 Datasheet, PDF (60/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
4.5.5 Data direction registers (DDRA, DDRB and DDRC)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0004
0000 0000
$0005
0000 0000
$0006
0000 0000
4
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all ports as inputs.
4.6
Other port considerations
All output ports can emulate ‘open-drain’ outputs. This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.
When using a port pin as an ‘open-drain’ output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the ‘open-drain’ is assigned and
the pin at this time is programmed as an input, it will read it as a ‘one’. The read-modify-write
instruction will then write this ‘one’ into the output data latch on the next cycle. This would cause
the ‘open-drain’ pin not to output a ‘zero’ when desired.
Note: ‘Open-drain’ outputs should not be pulled above V_DD.
INPUT/OUTPUT PORTS
MC68HC05X16
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