MC68HC05X16 Datasheet, PDF (110/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see Figure 7-7).
Data
RDI
Expected stop
Artificial edge
Data
Start bit
Data samples
a) Case 1: receive line low during artificial edge
Data
RDI
Expected stop
Start edge
Data
Start bit
7
Data samples
b) Case 2: receive line high during expected start edge
Figure 7-6 Artificial start following a framing error
Expected stop
Break
RDI
Detected as valid start edge
Start bit
Data samples
Start Start edge
qualifiers verification
samples
Figure 7-7 SCI start bit following a break
7.9
Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in Section 7.5 and shown in Figure 7-3. The transmitter
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
SERIAL COMMUNICATIONS INTERFACE
MC68HC05X16
For More Information On This Product,
Rev. 1
Go to: www.freescale.com