MC68HC05X16 Datasheet, PDF (57/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
A mask option is provided to enable resistive pull downs on all port B pins that are programmed
as inputs.
4.3
Port C
In addition to the standard port functions described for ports A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
4
the output data latch. The other port C pins are not affected by this feature.
A mask option is provided to enable resistive pull downs on all port C pins that are programmed
as inputs.
EEPROM/ECLK control
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0007 0
0
0
0 ECLK E1ERA E1LAT E1PGM 0000 0000
ECLK — External clock option bit
1 (set) – ECLK CPU clock is output on PC2.
0 (clear) – ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in Figure 4-2.
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Figure 4-2 ECLK timing diagram
MC68HC05X16
INPUT/OUTPUT PORTS
For More Information On This Product,
4-3
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