MC68HC05X16 Datasheet, PDF (143/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
10.2.1 Interrupt priorities
Each potential interrupt source is assigned a priority level, which means that if more than one
interrupt is pending at the same time, the processor will service the one with the highest priority
first. For example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
Table 10-2 shows the relative priority of all the possible interrupt sources. Figure 10-4 shows the
interrupt processing flow.
Table 10-2 Interrupt priorities
Source
Register Flags
Reset
—
—
Software interrupt (SWI)
—
—
External interrupt (IRQ) or WOI —
—
Timer input captures
TSR ICF1, ICF2
Timer output compares
TSR OCF1, OCF2
Timer overflow
TSR
TOF
Serial communications
interface (SCI)
SCSR
TDRE, TC,
OR, RDRF,
IDLE
MCAN
CINT
WIF,OIF,EIF,
TIF, RIF
Vector address Priority
$3FFE, $3FFF highest
$3FFC, $3FFD
$3FFA, $3FFB
$3FF8, $3FF9
$3FF6, $3FF7
$3FF4, $3FF5
$3FF2, $3FF3
$3FF0, $3FF1 lowest
10.2.2 Nonmaskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
10
10.2.3 Maskable hardware interrupts
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
MC68HC05X16
RESETS AND INTERRUPTS
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10-9
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