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MC68HC05X16 Datasheet, PDF (138/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit
Freescale Semiconductor, Inc.
Main CPU
clock
S
R
Latch
fosc/2 ÷ 4
fosc/32 prescaler
÷ 256
(Bit 7 of free
running counter)
÷ 7 watchdog
counter
Power-on
Reset
pin
WDOG bit
Control logic
Schmitt
trigger
Input
protection
Figure 10-3 Watchdog system block diagram
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see Section 1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit in
the miscellaneous register at $000C (see Section 10.1.2). Once enabled, the watchdog system
cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this
bit clears the counter to its initial value and prevents a watchdog timeout.
10
WDOG — Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set) – Watchdog enabled and counter cleared.
0 (clear) – The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
The divide-by-7 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time tDOG since the last clear or since the enable of the watchdog
counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than tDOG.
The reset generated by the watchdog system is apparent at the RESET pin (see Figure 10-3). The
RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’
for a minimum of tDOGL, the RESET pin is released.
RESETS AND INTERRUPTS
MC68HC05X16
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Rev. 1
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