MC68HC05X16 Datasheet, PDF (34/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
OSC1
OSC2
2
pin
pin
Oscillator
f_OSC
÷ 2, 4,
8 and 10
÷ 16
÷2
MCAN
SM–bit
(bit 1, $000C)
Control logic
Note:
The MCAN module clock is unaffected during SLOW mode.
Main internal clock
Figure 2-5 Slow mode divider block diagram
2.2.3.1 Miscellaneous register
Miscellaneous
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C POR INTP INTN INTE SFA SFB SM WDOG u001 000u
SM — Slow mode
1 (set)
– The system runs at a bus speed 16 times lower than normal (f_OSC/32,
/64, /128 or /160). SLOW mode affects all sections of the device
(including SCI, A/D and timer) except for the MCAN module.
0 (clear) – The system runs at normal bus speed (f_OSC/2, /4, /8 or /10).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
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Rev. 1
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