MC68HC05X16 Datasheet, PDF (196/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
B.7
Mask option register (MOR)
Mask option register (MOR)⁽¹⁾
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$7FDE WOI DIV2 DIV8 RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits. However, please read the important note on page B-1.
WOI — Wired-OR interrupt enable
1 (set) – Wired-OR interrupts are enabled, provided the WOIE bit in the
EPROM/EEPROM/ECLK control register is set.
0 (clear) – Wired-OR interrupts are disabled, irrespective of the WOIE bit in the
EPROM/EEPROM/ECLK control register.
The WOI bit can be used to enable the wired-OR interrupt (WOI) on all port B pins that have been
programmed as inputs. WOI is activated if the WOI bit is set and if the WOIE bit in the OPTR
register is also set.
DIV2, DIV8 — Clock divide ratio selection
The DIV2 and DIV8 bits are used to select the CPU clock divide ratio (see Table B-4). Note that a
divide-by-two clock ratio is forced in bootstrap mode, regardless of the DIV2 and DIV8 values.
Table B-4 Clock divide ratio selection
DIV2
DIV8 Clock divide ratio
1
1
2
1
0
4
0
1
8
0
0
10
RTIM — Reset time
This bit can modify the time t_PORL, where the RESET pin is kept low after a power-on reset.
1 (set) – t_PORL = 16 cycles.
0 (clear) – t_PORL = 4064 cycles.
RWAT — Watchdog after reset
This bit can modify the status of the watchdog counter after reset.
1 (set) – The watchdog will be active immediately following power-on or
external reset (except in bootstrap mode).
0 (clear) – The watchdog system will be disabled after power-on or external reset.
15
MC68HC705X32
MC68HC05X16
For More Information On This Product,
Rev. 1
Go to: www.freescale.com