MC68HC05X16 Datasheet, PDF (74/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
5.3.4 MCAN interrupt register (CINT)
All bits of this register are read only; all are cleared by a read of the register.
This register must be read in the interrupt handling routine in order to enable further interrupts.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset condition
State
on reset
MCAN interrupt
(CINT)
$0023
External reset - - - 0 0000
WIF OIF EIF TIF RIF
RR bit set - - - u 0u00
5
WIF — Wake-up interrupt flag
If the MCAN detects bus activity whilst it is asleep, it clears the SLEEP bit in the CCOM register;
the WIF bit will then be set. WIF is cleared by reading the MCAN interrupt register (CINT), or by
an external reset.
1 (set) – MCAN has detected activity on the bus and requested wake-up.
0 (clear) – No wake-up interrupt has occurred.
OIF — Overrun interrupt flag
When OIE is set then this bit will be set when a data overrun condition is detected. Like all the bits
in this register, OIF is cleared by reading the register, or when reset request is set.
1 (set) – A data overrun has been detected.
0 (clear) – No data overrun has occurred.
EIF — Error interrupt flag
When EIE is set then this bit will be set by a change in the error or bus status bits in the MCAN
status register. Like all the bits in this register, EIF is cleared by reading the register, or by an
external reset.
1 (set) – There has been a change in the error or bus status bits in CSTAT.
0 (clear) – No error interrupt has occurred.
TIF — Transmit interrupt flag
The TIF bit is set at the end of a transmission whenever both the TBA and TIE bits are set. Like all
the bits in this register, TIF is cleared by reading the register, or when reset request is set.
1 (set) – Transmission complete, the transmit buffer is accessible.
0 (clear) – No transmit interrupt has occurred.
MOTOROLA CAN MODULE (MCAN)
MC68HC05X16
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Rev. 1
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