MC68HC05X16 Datasheet, PDF (80/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
5.3.9 MCAN output control register (COCNTRL)
This register allows the setup of different output driver configurations under software control. The
user may select active pull-up, pull-down, float or push-pull output.
Note:
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
5
MCAN output control (COCNTRL) $0028 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCM1 OCM0 Undefined
OCM1 and OCM0 — Output control mode bits
The values of these two bits determine the output mode, as shown in Table 5-4.
Table 5-4 Output control modes
OCM1
0
0
1
1
OCM0
0
1
0
1
Function
Biphase mode
Not used
Normal mode 1
Bit stream transmitted on both TX0 and TX1
Normal mode 2
TX0 - bit sequence
TX1 - bus clock (t_xclk)
Note:
The transmit clock (t_xclk) is used to indicate the end of the bit time and will be high during
the SYNC_SEG.
For all the following modes of operation, a dominant bit is internally coded as a zero, a
recessive as a one. The other output control bits are used to determine the actual
voltage levels transmitted to the MCAN bus for dominant and recessive bits.
Biphase mode
If the CAN modules are isolated from the bus lines by a transformer then the bit stream has to be
coded so that there is no resulting dc component. There is a flip-flop within the MCAN that keeps
the last dominant configuration; its direct output goes to TX0 and its complement to TX1. The
flip-flop is toggled for each dominant bit; dominant bits are thus sent alternately on TX0 and TX1;
i.e. the first dominant bit is sent on TX0, the second on TX1, the third on TX0 and so on. During
recessive bits, all output drivers are deactivated (i.e. high impedance).
MOTOROLA CAN MODULE (MCAN)
MC68HC05X16
For More Information On This Product,
Rev. 1
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