MC68HC05X16 Datasheet, PDF (30/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
2.2
Low power modes
2
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.2.1 STOP mode
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off (providing the MCAN is ‘asleep’, see Section 5.5) halting all internal
processing including timer, serial communications interface and the A/D converter (see flow chart
in Figure 2-4). The MCU will wake up from STOP mode only by receipt of an MCAN external
interrupt or by the detection of a reset (logic low on RESET pin or a power-on reset.
The STOP instruction can be executed (i.e. the oscillator can be turned off) only when the MCAN
module is in SLEEP mode. See Section 5.5.
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section 11.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count
while exiting STOP mode (see Section 2.2.3).
All other registers and memory remain unaltered and all input/output lines remain unchanged. This
continues until a MCAN interrupt, wired-OR interrupt, external interrupt (IRQ) or reset is sensed,
at which time the internal oscillator is turned on. The interrupt or reset causes the program counter
to vector to the corresponding locations ($3FFA, B and $3FFE, F respectively).
When leaving STOP mode, a t_PORL internal cycles delay is provided to give the oscillator time to
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either 16
or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by
fetching the reset vector, if reset wakes it up.
Note:
If t_PORL is selected to be 16 cycles, it is recommended that an external clock signal is
used to avoid problems with oscillator stability while the device is in STOP mode.
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the modules of the MC68HC05X16.
– The watchdog timer is reset; see Section 10.1.4.1
– The EEPROM acts as read-only memory (ROM); see Section 3.6
– All SCI activity stops; see Section 7.13
– The timer stops counting; see Section 6.6
– The PLM outputs remain at current levels; see Section 8.3
– The A/D converter is disabled; see Section 9.3
– The I-bit in the CCR is cleared
MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
For More Information On This Product,
Rev. 1
Go to: www.freescale.com