MC68HC05X16 Datasheet, PDF (141/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
10.2
Interrupts
The MCU can be interrupted by five different sources: three maskable hardware interrupts, one
non maskable software interrupt and one maskable MCAN interrupt:
• External signal on the IRQ pin, WOI on port B pins or NWOI pin
• Serial communications interface (SCI)
• Programmable timer
• Software interrupt instruction (SWI)
• MCAN interrupt (CIRQ)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on
the stack.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note:
Power-on and external reset clear all interrupt enable bits to prevent interrupts during
the reset sequence, but set the INTE bit (see Section 3.8).
10
MC68HC05X16
RESETS AND INTERRUPTS
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10-7
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