MC68HC05X16 Datasheet, PDF (73/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
TCS — Transmission complete status
This bit is cleared by the MCAN when TR becomes set. When TCS is set it indicates that the last
requested transmission was successfully completed. If, after TCS is cleared, but before
transmission begins, an abort transmission command is issued then the transmit buffer will be
released and TCS will remain clear. TCS will then only be set after a further transmission is both
requested and successfully completed.
1 (set) – Complete – Last requested transmission successfully completed.
0 (clear) – Incomplete – Last requested transmission not complete.
TBA — Transmit buffer access
When clear, the transmit buffer is locked and cannot be accessed by the CPU. This indicates that
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either a message is being transmitted, or is awaiting transmission. If the CPU writes to the transmit
buffer while it is locked, then the bytes will be lost without this being signalled.
1 (set) – Released – The transmit buffer may be written to by the CPU.
0 (clear) – Locked – The CPU cannot access the transmit buffer.
DO — Data overrun
This bit is set when both receive buffers are full and there is a further message to be stored. In this
case the new message is dropped, but the internal logic maintains the correct protocol. The MCAN
does not receive the message, but no warning is sent to the transmitting node. The MCAN clears
DO when the CPU sets the COS bit in the CCOM register.
Note that data overrun can also be caused by a transmission, since the MCAN will temporarily
store an outgoing frame in a receive buffer in case arbitration is lost during transmission.
1 (set) – Overrun – Both receive buffers were full and there was another
message to be stored.
0 (clear) – Normal operation.
RBS — Receive buffer status
This bit is set by the MCAN when a new message is available. When clear this indicates that no
message has become available since the last RRB command. The bit is cleared when RRB is set.
However, if the second receive buffer already contains a message, then control of that buffer is
given to the CPU and RBS is immediately set again. The first receive buffer is then available for
the next incoming message from the MCAN.
1 (set) – Full – A new message is available for the CPU to read.
0 (clear) – Empty – No new message is available.
MC68HC05X16
MOTOROLA CAN MODULE (MCAN)
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