MC68HC05X16 Datasheet, PDF (145/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
Note:
If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
interrupt which is not latched); therefore, only one external interrupt pulse can be
latched during t_ILIL and serviced as soon as the I-bit is cleared.
10.2.3.2 External interrupts
IRQ interrupt
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit
(INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by
the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and
INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is
recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks
further interrupts until the present one is serviced. The external interrupt service routine address
is specified by the content of memory locations $3FFA and $3FFB.
Wired-OR interrupt (WOI)
An external WOI capability is provided on all port B I/O pins when they are programmed as inputs,
and on the NWOI pin. A WOI is activated only if WOIE in the EEPROM control register is set and
if wired-OR interrupts have been chosen as an option on the device (see Section 1.2). If wired-OR
interrupts are enabled on a given input pin (NWOI pin or port B pins; refer to Section 2.3.19 and
Section 4.2), an external interrupt is requested when this pin is pulled high. The request is serviced
by the interrupt routine whose start address is contained in memory locations $3FFA and $3FFB.
External and power-on reset clear the WOIE bit. A WOI interrupt will cause the MCU to exit STOP
mode.
The interrupt enable bit (INTE) in the miscellaneous register enables both wired-OR interrupts and
the IRQ interrupt. IRQ and WOI are internally OR-ed before interrupt sensitivity selection (see
Section 10.2.3.1).
10
10.2.3.3 MCAN interrupt (CIRQ)
Several sources can trigger a CIRQ. The MCAN interrupt register at $0023 is used to identify the
source. Each CIRQ source can be individually enabled (except the wake-up interrupt, which is
always enabled) by different bits of the MCAN control register at $0020.
The CIRQ sources are (also see Section 5.3.4):
Receive IRQ: this signals successful reception of a complete message.
Transmit IRQ: this signals successful transmission of a complete message.
MC68HC05X16
RESETS AND INTERRUPTS
For More Information On This Product,
Go to: www.freescale.com
10-11