MC68HC05X16 Datasheet, PDF (144/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
10.2.3.1 Miscellaneous register
Miscellaneous
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000C POR INTP INTN INTE SFA SFB SM WDOG u001 000u
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ and WOI pins are sensitive to as shown
in Table 10-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or
external reset. Therefore the device is initialised with negative edge and low level sensitivity.
Table 10-3 IRQ and WOI sensitivity
INTP
0
0
1
1
INTN
IRQ sensitivity
0
Negative edge and low level
sensitive
1 Negative edge only
0 Positive edge only
1
Positive and negative edge
sensitive
WOI interrupt sensitivity
Positive edge and high level
sensitive
Positive edge only
Negative edge only
Positive and negative edge
sensitive
10
Interrupt sensitivity options selected by INTP and INTN of the miscellaneous register apply to
external interrupt signal, EI. EI is an OR function of all enabled WOI pins (port B and NWOI) and
of the inverted value of the IRQ pin. When one WOI pin is high, it masks any subsequent edge or
level on any other EI pin (IRQ, port B or NWOI).
INTE — External interrupt enable
1 (set) – External interrupt (IRQ) and wired-OR interrupt (WOI) enabled.
0 (clear) – External interrupt (IRQ) and wired-OR interrupt (WOI) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 10-3 describes the various triggering options available for the IRQ and WOI pins, however it
is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is
possible to change the external interrupt options only while the I-bit is set. Any attempt to change
the external interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is
pending, it will automatically be cleared when selecting a different interrupt option.
RESETS AND INTERRUPTS
MC68HC05X16
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