MC68HC05X16 Datasheet, PDF (188/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
Table B-1 Register outline
Register name
Address bit 7 bit 6 bit 5 bit 4 bit 3
bit 2
bit 1
bit 0
State on
reset
Port A data (PORTA)
$0000
Undefined
Port B data (PORTB)
$0001
Undefined
Port C data (PORTC)
$0002
PC2/ECLK
Undefined
Port D data (PORTD)
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Port A data direction (DDRA) $0004
0000 0000
Port B data direction (DDRB) $0005
0000 0000
Port C data direction (DDRC) $0006
0000 0000
EEPROM/ECLK control
$0007 WOIE CAF E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA)
$0008
0000 0000
A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A
0000 0000
Pulse length modulation B (PLMB) $000B
Miscellaneous
$000C POR⁽¹⁾ INTP INTN INTE SFA SFB
0000 0000
SM WDOG⁽²⁾ u001 000u
SCI baud rate (BAUD)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
SCI control 1 (SCCR1)
$000E R8 T8
M WAKE CPOL CPHA LBCL Undefined
SCI control 2 (SCCR2)
$000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000
SCI status (SCSR)
$0010 TDRE TC RDRF IDLE OR NF FE
1100 000u
SCI data (SCDR)
$0011
0000 0000
Timer control (TCR)
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
Timer status (TSR)
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Input capture high 1
$0014
Undefined
Input capture low 1
$0015
Undefined
Output compare high 1
$0016
Undefined
Output compare low 1
$0017
Undefined
Timer counter high
$0018
1111 1111
Timer counter low
$0019
1111 1100
Alternate counter high
$001A
1111 1111
Alternate counter low
$001B
1111 1100
Input capture high 2
$001C
Undefined
Input capture low 2
$001D
Undefined
Output compare high 2
$001E
Undefined
Output compare low 2
$001F
Undefined
Options (OPTR)⁽³⁾
$0100
EE1P SEC Not affected
Mask option register (MOR)⁽⁴⁾ $7FDE WOI DIV2 DIV8 RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits. However, please read the important note on page
B-1.
15
MC68HC705X32
MC68HC05X16
For More Information On This Product,
Rev. 1
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