MC68HC05X16 Datasheet, PDF (54/232 Pages) Freescale Semiconductor, Inc – High-density complementary metal oxide semiconductor HCMOS) microcontroller unit

Freescale Semiconductor, Inc.
SFB — Slow or fast mode selection for PLMB (see Section 8.1)
1 (set) – Slow mode PLMB (4096 x timer clock period).
0 (clear) – Fast mode PLMB (256 x timer clock period).
3
Note:
The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA
bit and the SFB bit to the desired values before writing to the PLM registers; not doing
so could temporarily give incorrect values at the PLM outputs.
SM — Slow mode (see Section 2.2.3)
1 (set)
– The system runs at a bus speed 16 times lower than normal
(f_OSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f_OSC/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG — Watchdog enable/disable (see Section 10.1.4)
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set) – Watchdog counter cleared and enabled.
0 (clear) – The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
MEMORY AND REGISTERS
MC68HC05X16
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