MC68HC908GR8 Datasheet, PDF (64/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Break Module (BRK)
IAB15–IAB8
IAB15–IAB0
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BREAK
IAB7–IAB0
Figure 6-1. Break Module Block Diagram
Addr. Register Name
Bit 7
6
5
4
3
2
Read: 0
0
0
1
0
0
$FE00
SIM Break Status Register
(SBSR)
Write:
R
R
R
R
R
R
Reset: 0
0
0
1
0
0
Read:
$FE03
SIM Break Flag Control
Register (SBFCR)
Write:
BCFE
R
R
R
R
R
Reset: 0
Read:
$FE09
Break Address Register High
(BRKH)
Write:
Bit 15
14
13
12
11
10
Reset: 0
0
0
0
0
0
Read:
$FE0A
Break Address Register Low
(BRKL)
Write:
Bit 7
6
5
4
3
2
Reset: 0
0
0
0
0
0
Read:
0
0
0
0
$FE0B
Break Status and Control
Register (BRKSCR)
Write:
BRKE
BRKA
Reset: 0
0
0
0
0
0
Note: Writing a logic 0 clears BW.
= Unimplemented
R = Reserved
Figure 6-2. I/O Register Summary
1
BW
NOTE
0
R
Bit 0
0
R
0
R
9
Bit 8
0
0
1
Bit 0
0
0
0
0
0
0
6.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
64
Freescale Semiconductor