MC68HC908GR8 Datasheet, PDF (188/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 19-1. SIM Block Diagram
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
Addr. Register Name
Bit 7
6
5
4
3
Read:
$FE00
SIM Break Status Register
(SBSR)
Write:
R
R
R
R
R
Reset: 0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
Read: POR
PIN
COP
ILOP
ILAD
$FE01
SIM Reset Status Register
(SRSR)
Write:
POR: 1
0
0
0
0
Read:
$FE03
SIM Break Flag Control Reg-
ister (SBFCR)
Write:
BCFE
R
R
R
R
Reset: 0
= Unimplemented
Figure 19-2. SIM I/O Register Summary
2
1
SBSW
R
NOTE
0
0
MODRST LVI
0
0
R
R
Bit 0
R
0
0
0
R
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
188
Freescale Semiconductor