MC68HC908GR8 Datasheet, PDF (133/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Functional Description
The monitor code has been updated from previous versions to allow enabling the PLL to generate the
internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency
crystal. This addition, which is enabled when IRQ is held low out of rest, is intended to support serial
communication/ programming at 9600 baud in monitor mode by stepping up the external frequency
(assumed to be 32.768 kHz) by a fixed amount to generate the desired internal frequency (2.4576 MHz).
Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset
vector is not blank because entry into monitor mode in this case requires V_TST on IRQ.
15.3.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
1. If $FFFE and $FFFF contain values not cared:
– The external clock is 9.8304 MHz
– IRQ = V_TST (PLL off)
2. If $FFFE and $FFFF contain $FF, blank state:
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ pullup; PLL off)
3. If $FFFE and $FFFF contain $FF, blank state:
– The external clock is 32.768 kHz (crystal)
– IRQ = V_SS (this setting initiates the PLL to boost the external 32.768 kHz to an internal bus
frequency of 2.4576 MHz)
If entering monitor mode with V_TST applied on IRQ (condition set 1), the CGMOUT frequency is equal to
the CGMXCLK frequency and the OSC1 input directly generates internal bus clocks. In this case, the
OSC1 signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage applied on IRQ (condition set 2 or 3, where applied voltage
is either V_DD or V_SS), then all port B pin requirements and conditions, are not in effect. This is to reduce
circuit requirements when performing in-circuit programming.
NOTE
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial POR reset. Once the part has been
programmed, the traditional method of applying a voltage, V_TST, to IRQ
must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these conditions:
• If monitor mode was entered as a result of the reset vector being blank (condition set 2 or 3), the
COP is always disabled regardless of the state of IRQ or RST.
• If monitor mode was entered with V_TST on IRQ (condition set 1), then the COP is disabled as long
as V_TST is applied to either IRQ or RST.
The second condition states that as long as V_TST is maintained on the IRQ pin after entering monitor
mode, or if V_TST is applied to RST after the initial reset to get into monitor mode (when V_TST was applied
to IRQ), then the COP will be disabled. In the latter situation, after V_TST is applied to the RST pin, V_TST
can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor
mode.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
133