MC68HC908GR8 Datasheet, PDF(134/286 Page) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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MC68HC908GR8 Datasheet, PDF (134/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

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Monitor ROM (MON)

Table 15-1. Monitor Mode Signal Requirements and Options

IRQ

RESET

$FFFE/

$FFFF

External

PLL PTB0 PTB1 Clock(1) CGMOUT

Bus

Freq

COP

For Serial

Communication

Baud

PTA0 PTA1 Rate(2) (3)

Comment

X GND

X

X

X

X

X

No operation

0

0 Disabled X

X

0

until reset goes

high

VTST

VDD

or

VTST

X OFF 1

1

0

0

9.8304

MHz

4.9152

MHz

2.4576

MHz

Disabled

X

1

9600

DNA

PTB0 and PTB1

voltages only

required if

IRQ = VTST

VDD VDD $FFFF OFF X

X

9.8304

MHz

4.9152

MHz

2.4576

MHz

Disabled

1

X

0

1

9600

DNA

External

frequency always

divided by 4

GND VDD $FFFF ON X

X

32.768

kHz

4.9152

MHz

2.4576

MHz

Disabled

1

X

0

1

9600

DNA

PLL enabled

(BCS set) in

monitor code

VDD

or VTST $FFFF OFF X

X

X

GND

Enters user

mode â will

â

â Enabled X

X

â

encounter an

illegal address

reset

VDD

or

GND

VDD

or

VTST

Not

$FFFF

OFF

X

X

X

â

â Enabled X

X

â

Enters

user mode

1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator

2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication

3. PTA1 = 0 â serial, PTA1 = 1 â parallel communication for security code entry

4. DNA = does not apply, X = donât care

Figure 15-2 shows a simplified diagram of the monitor mode entry when the reset vector is blank and just

1 x VDD voltage is applied to the IRQ pin. An external oscillator of 9.8304 MHz is required for a baud rate

of 9600, as the internal bus frequency is automatically set to the external frequency divided by four.

Enter monitor mode with pin configuration shown in Figure 15-1 by pulling RST low and then high. The

rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins

can change.

Once out of reset, the MCU waits for the host to send eight security bytes. (See Security.) After the

security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is

ready to receive a command.

NOTE

The PTA1 pin must remain at logic 0 for 24 bus cycles after the RST pin

goes high to enter monitor mode properly.

MC68HC908GR8 â¢ MC68HC908GR4 Data Sheet, Rev. 7

134

Freescale Semiconductor

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