MC68HC908GR8 Datasheet, PDF (53/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

4.3.2.9 KBD0–KBD4 Pins
A 0 on a keyboard interrupt pin latches an external interrupt request.
Interrupts
4.3.2.10 ADC (Analog-to-Digital Converter)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled.
4.3.2.11 TBM (Timebase Module)
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
4.3.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 4-2. Interrupt Source Flags
Interrupt Source
Reset
SWI instruction
IRQ pin
CGM (PLL)
TIM1 channel 0
TIM1 channel 1
TIM1 overflow
TIM2 channel 0
Reserved
TIM2 overflow
SPI receive
SPI transmit
SCI error
SCI receive
SCI transmit
Keyboard
ADC conversion complete
Timebase
Interrupt Status Register Flag
—
—
IF1
IF2
IF3
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
IF12
IF13
IF14
IF15
IF16
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
53