MC68HC908GR8 Datasheet, PDF (191/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Reset and System Initialization
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 19-4. External Reset Timing
19.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
at which point the reset vector will be fetched. See Figure 19-5. An internal reset can be caused by an
illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 19-6.
NOTE
For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 19-5.
IRST
RST
CGMXCLK
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
VECTOR HIGH
Figure 19-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
MODRST
INTERNAL RESET
Figure 19-6. Sources of Internal Reset
Table 19-2. PIN Bit Set Timing
Reset Recovery
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
191