MC68HC908GR8 Datasheet, PDF (252/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Electrical Specifications
Characteristic⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Unit
Pullup resistors (as input only)
Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0,
PTD6/T2CH0–PTD0/SS
R_PU
20
45
65
kΩ
Capacitance
Ports (as input or output)
C_Out
—
C_In
—
—
—
12
8
pF
Monitor mode entry voltage
V_TST
V_DD +2.5
—
V_DD +4.0
V
Low-voltage inhibit, trip falling voltage – target
V_TRIPF
2.35
2.60
2.70
V
Low-voltage inhibit, trip rising voltage – target
V_TRIPR
2.45
2.66
2.80
V
Low-voltage inhibit reset/recover hysteresis – target
(V_TRIPF + V_HYS = V_TRIPR)
V_HYS
—
60
—
mV
Input hysteresis (alternative input functions only)^{(7), (12)}
V_InHYS
0.06 x V_DD
—
—
V
POR rearm voltage^{(7), (13)}
V_POR
0
—
100
mV
POR reset voltage⁽¹⁴⁾
V_PORRST
0
700
800
mV
POR rise time ramp rate^{(7), (15)}
R_POR
0.035
—
—
V/ms
1. V_DD = 3.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I_DD measured using external square wave clock source (f_osc = 16.4 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I_DD. Measured with all modules enabled.
4. Wait I_DD measured using external square wave clock source (f_osc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
I_DD. Measured with PLL and LVI enabled.
5. Stop I_DD is measured with OSC1 = V_SS.
6. Stop I_DD with TBM enabled is measured using an external square wave clock source (f_OSC = 32.8 KHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs.
7. This parameter is characterized and not tested on each device.
8. All functional non-supply pins are internally clamped to V_SS and V_DD.
9. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
10. Power supply must maintain regulation within operating V_DD range during instantaneous and operating maximum current
conditions. If positive injection current (V_IN > V_DD) is greater than I_DD, the injection current may flow out of V_DD and could
result in external power supply going out of regulation. Ensure external V_DD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
11. Pullups and pulldowns are disabled.
12. Digital inputs have hysteresis whenever they are configured for any alternative peripheral input function other than as a
general-purpose input.
13. Maximum is highest voltage that POR is guaranteed.
14. Maximum is highest voltage that POR is possible.
15. If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V_DD is reached.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
252
Freescale Semiconductor