MC68HC908GR8 Datasheet, PDF (33/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Register Summary
Addr.
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
↓
$0035
$0036
$0037
Register Name
Read:
Timer 1 Channel 1
Register Low (T1CH1L)
Write:
Reset:
Read:
Timer 2 Status and Control
Register (T2SC)
Write:
Reset:
Read:
Timer 2 Counter Register
High (T2CNTH)
Write:
Reset:
Read:
Timer 2 Counter Register
Low (T2CNTL)
Write:
Reset:
Read:
Timer 2 Counter Modulo
Register High (T2MODH)
Write:
Reset:
Read:
Timer 2 Counter Modulo
Register Low (T2MODL)
Write:
Reset:
Timer 2 Channel 0 Status ^Read:
and Control Register Write:
(T2SC0) _Reset:
Read:
Timer 2 Channel 0
Register High (T2CH0H)
Write:
Reset:
Read:
Timer 2 Channel 0
Register Low (T2CH0L)
Write:
Reset:
Read:
Unimplemented
Write:
Reset:
Read:
PLL Control Register
(PCTL)
Write:
Reset:
Read:
PLL Bandwidth Control
Register (PBWC)
Write:
Reset:
Bit 7
Bit 7
TOF
0
0
Bit 15
0
Bit 7
0
Bit 15
1
Bit 7
1
CH0F
0
0
Bit 15
Bit 7
0
PLLIE
0
AUTO
0
6
5
4
3
2
1
6
5
4
3
2
1
Indeterminate after reset
0
0
TOIE TSTOP
TRST
PS2
PS1
0
1
0
0
0
0
14
13
12
11
10
9
0
0
0
0
0
0
6
5
4
3
2
1
0
14
1
6
1
CH0IE
0
14
6
0
0
0
0
13
12
11
10
1
1
1
1
5
4
3
2
1
1
1
1
MS0B MS0A ELS0B ELS0A
0
0
0
0
13
12
11
10
Indeterminate after reset
5
4
3
2
Indeterminate after reset
0
9
1
1
1
TOV0
0
9
1
0
0
0
PLLF
PLLON
BCS
0
PRE1
0
1
0
0
LOCK
0
0
ACQ
0
0
= Unimplemented
0
0
R = Reserved
0
PRE0
0
0
0
VPR1
0
0
0
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
Bit 0
Bit 0
PS0
0
Bit 8
0
Bit 0
0
Bit 8
1
Bit 0
1
CH0MAX
0
Bit 8
Bit 0
0
VPR0
0
R
0
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
33