MC68HC908GR8 Datasheet, PDF (149/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Port B
16.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1
to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0005
Bit 7
0
6
5
4
3
2
1
0
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
0
0
0
= Unimplemented
Figure 16-7. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB5–DDRB0 — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB5–DDRB0], configuring all port
B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
NOTE
For those devices packaged in a 28-pin DIP and SOIC package, PTB5,4
are not connected. Set DDRB5,4 to a 1 to configure PTB5,4 as outputs.
Figure 16-8 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 16-8. Port B I/O Circuit
When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-3 summarizes the operation of the port B pins.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
Freescale Semiconductor
149