MC68HC908GR8 Datasheet, PDF (118/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

External Interrupt (IRQ)
ACK
RESET
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
D ^CLR Q
CK
IRQ
FF
SYNCHRO-
NIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
Addr.
$001D
Register Name
Read:
IRQ Status and Control
Register (INTSCR)
Write:
Reset:
Bit 7
0
0
6
5
0
0
0
0
= Unimplemented
4
3
0
IRQF
0
0
Figure 12-2. IRQ I/O Register Summary
2
1
Bit 0
0
IMASK MODE
ACK
0
0
0
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt remains set until both of
the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to high level
The vector fetch or software clear may occur before or after the interrupt pin returns to high level. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
118
Freescale Semiconductor