MC68HC908GR8 Datasheet, PDF (194/286 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

System Integration Module (SIM)
19.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 19.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 19.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
19.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
19.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 19-8 shows
interrupt entry timing. Figure 19-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). See Figure 19-10.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
IDB
DUMMY PC–1[7:0] PC–1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
R/W
MODULE INTERRUPT
Figure 19-8. Interrupt Entry Timing
I BIT
IAB
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
IDB
CCR
A
X
PC – 1 [7:0] PC–1[15:8] OPCODE OPERAND
R/W
Figure 19-9. Interrupt Recovery Timing
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
194
Freescale Semiconductor